1. Field of the Invention
The present invention relates to implementation of burst mode operation in a memory device.
2. Description of the Related Art
In electronic memory devices, burst mode generally refers to the operation of accessing multiple memory addresses within a memory array with a single command and address identifier in order to read or write a considerable amount of data rapidly. The amount of data accessed with each read or write command sent to the memory device is determined by the burst length, which corresponds to the number of data words to be read or written in a continuous stream, with one data word being accessed per successive clock edge. Without any burst mode capability, the burst length has a fixed value, and only a certain amount of data (e.g., a predetermined number of data words) is accessible with each read or write command. If each read or write command accesses only one or a few memory addresses, a lengthy sequence of commands would be necessary to read or write a large block of data, making memory access unacceptably cumbersome and slow.
Modern memory devices permit the burst length to be adjusted during operation to accommodate a range of memory access modes. For example, the burst length can be set to a small number where one or a few memory addresses need to be accessed and can be set to a larger number where a significant block of data, such as the entire contents of the memory array, must be accessed quickly. In typical memory devices, a mode register or comparable device maintains the current set of parameters by which data is written to and read from the memory array, including a burst length setting. To program the burst length to a particular value, a command must be sent to the memory device to adjust the mode register burst length setting to the appropriate value. This mode register set command must be sent to the memory device each time the burst length is changed, and with each change, access to the memory array must be temporarily halted to send the command and re-write the mode register burst mode setting. The need to program the mode register with each change of the burst length adds complexity to the controller responsible for generating and sending commands to the memory device. It would be desirable to implement a flexible burst mode capability in a memory device while minimizing the complexity of the memory access scheme and delays associated with changing the burst length.